This application claims the priority benefit of Taiwan application serial no. 90109498, filed Apr. 20, 2001.
1. Field of the Invention
The invention relates in general to an operation of a memory device, and more particularly, to a flash memory erase method.
2. Description of the Related Art
The flash memory is the most common non-volatile memory (NVM) and has a high device integration and an erase rate much higher than other kinds of non-volatile memories. In many flash memories, an erase operation is performed by applying a negative bias Vg to the gate of the memory cells thereof, and a positive bias Vd to the source/drain region. The difference between the biases Vg and Vd has to be sufficiently large to cause a tunneling effect such that the electron in the gate can tunnel to the substrate.
Due to the difference of process condition, the bias Vd required to erase the memory of each memory cell has a distribution range. The distribution range basically covers the erase voltage for most of the memories. Although a single value of Vd equal to or over the maximum of the distribution range can erase the memories of most memory cells, it is easy to damage the memory cells thereby. Therefore, the conventional erase method of the flash memory uses a step-by-step manner to increase the bias Vd applied to the source/drain region. After the end of each step, an inspection operation is performed until it is confirmed that all the memories of the memory cells have been erased.
The above method insures that the memory of all the memory cells has been erased. However, an inspection step is required each time after raising the bias Vd. As 10 Kbit or 100 Kbit is used as an inspection unit for the inspection operation, a very long time is consumed. Thus, the erase operation time cannot be shortened.
The invention provides a flash memory erase method. A bias Vg is applied to a gate of a memory cell, and a bias Vd is applied to a source/drain region of the memory cell to perform an erase operation. The bias Vd gradually increases from an initial value to a predetermined value. While increasing the bias Vg, no inspection step is performed. The memory cells are inspected to determine whether the memory thereof has been entirely erased. If yes, the erase operation is complete. If not, a voltage raise erase-inspection step is performed at least once until the memory of all the memory cells has been erased. The ith voltage raise erase-inspection step includes a voltage raise erase step for a time period T(i) and an inspection step afterwards. The bias Vd for the first voltage raise erase step is higher than the predetermined value. When i greater than 1, the bias Vd of the ith voltage raise erase step is higher than that of the (ixe2x88x921)th voltage raise erase step.
As mentioned above, in the flash memory erase method in the invention, while increasing the initial value of the bias Vd applied to the source/drain region to the predetermined value, no inspection step is required. The overall operation time for the erase operation is thus greatly reduced.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.